Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1990-10-30
1993-04-20
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 371 111, 371 102, G11C 2900
Patent
active
052048365
ABSTRACT:
An apparatus and method are disclosed for switching the arrays of parallel memory data structures upon the detection of defects in a memory storage device. To date, redundancy has been implemented using duplicate arrays connected to laser zappable fuses. The use of laser zappable fuses imposes restrictive technology constraints. In particular, to avoid damage to surrounding circuity when a fuse is "zapped," considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The present invention uses only two extra parallel arrays to correct for any open or short defects in a parallel memory data structure, and does it with a nearly constant array length as the original arrays. The redundant arrays as well as the original arrays are connected to toggle switches. Upon encountering any open or short in the one or more data paths, the toggle switches coupled to the open or short are "flipped" to connect to the adjacent data paths in a cascading fashion. The toggle switches are implemented as steering logic switches having NMOS and PMOS transistors in a CMOS array. The steering logic switches are controlled with a pointer register which can be implemented either by logically decoding the defect area or by actually implementing a shifter which stops when its state reaches the defect.
REFERENCES:
patent: 4739498 (1988-04-01), Eichhorn
patent: 5134584 (1992-07-01), Boler et al.
Popek Joseph A.
Sun Microsystems Inc.
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