Method and apparatus for implementing packet work area...

Details Method and apparatus for implementing packet work area... Method and apparatus for implementing packet work area...

2007-07-03

2007-07-03

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S154000

Reexamination Certificate

active

10427864

ABSTRACT:
A mapping area including a packet work area and a corresponding set of packet segment registers are provided. A packet segment register is loaded with a Packet ID (PID) and a packet translation unit maps packet data into the corresponding packet work area. Packets include one or more data buffers. Data buffers are chained together using a corresponding buffer descriptor for each data buffer. Each buffer descriptor points to the corresponding data buffer and to a next buffer descriptor. Each buffer descriptor includes an offset for a next packet data. A translate address is compared to the offset of each buffer descriptor to identify the data buffer containing the translate address. A buffer sharing counter (BSC) is allocated for a shared data buffer. Each buffer descriptor pointing to the shared data includes a pointer to the buffer sharing counter (BSC).

REFERENCES:
patent: 4902225 (1990-02-01), Lohn
patent: 6859454 (2005-02-01), Bowes
patent: 6981036 (2005-12-01), Hamada

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