Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1998-09-30
2003-07-01
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C709S249000, C710S120000
Reexamination Certificate
active
06587912
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory systems in computer systems. More specifically, the present invention relates to a method and apparatus for implementing multiple memory buses on a memory module.
BACKGROUND OF THE INVENTION
Memory modules such as the Dual In-Line Memory Module (DIMM) have become a popular memory packaging design. DIMMs are small printed circuit boards mounted with a plurality of memory devices. The more widely used DIMMs have 168 pins and can transfer 64 bits at a time. DIMMs have leads accessible via both sides of a printed circuit board's electrical connector unlike its predecessor, the Single In-Line Memory Module (SIMM), which has leads on only one side of the printed circuit board's electrical connector. DIMMs are inserted into small socket connectors that are soldered onto a larger printed circuit board, or motherboard. Because DIMMs are socketed, they are inherently replaceable and upgradable. The DIMMs are typically connected in parallel to a memory controller via a single memory bus. The memory controller coordinates movement of data between memory devices on the DIMMs and the other components on the computer system via the single memory bus.
One drawback to memory systems implementing memory modules was that the memory systems were limited to the number of memory devices that may be connected to the memory bus. Thus, regardless of the number of memory devices that were mountable on a memory module and the number of socket connectors that were mountable on a motherboard, the capacity of the memory system was limited by the constraint imposed by the memory bus.
SUMMARY
A memory repeater has a first I/O port and a second I/O port. The memory repeater first I/O port is coupled to a first memory bus. The memory repeater second I/O port is coupled is series to a second memory bus.
REFERENCES:
patent: 5590299 (1996-12-01), Bennett
patent: 5854790 (1998-12-01), Scott et al.
patent: 5857109 (1999-01-01), Taylor
patent: 5860080 (1999-01-01), James et al.
patent: 6006276 (1999-12-01), Picazo, Jr.
patent: 6073251 (2000-06-01), Jewett et al.
patent: 6185644 (2001-02-01), Farmwald et al.
patent: 6226762 (2001-05-01), Foote et al.
patent: 6240526 (2001-05-01), Petivan et al.
Bonella Randy
Horine Bryce D.
Leddige Michael W.
MacWilliams Peter D.
Blakely , Sokoloff, Taylor & Zafman LLP
Bragdon Reginald G.
Intel Corporation
Vital Pierre M.
LandOfFree
Method and apparatus for implementing multiple memory buses... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for implementing multiple memory buses..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for implementing multiple memory buses... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3052218