Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-05-10
2001-09-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S037000, C326S049000, C326S042000
Reexamination Certificate
active
06285218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to programmable logic circuits, and in particular, to dynamic programmable logic gates using mask-programmable logic cells.
2. Description of the Related Art
Logic circuits, particularly those used to simultaneously evaluate an equation with a large number of inputs have been implemented in a variety of architectures. A programmable logic array (PLA) is an integrated circuit device that incorporates fixed sets of AND and OR logic gates or similar functions such as NAND, NOR, XOR or XNOR with one or more interconnect planes used to create several logical combinatorial outputs from several logical inputs. The interconnect planes in a mask PLA are usually metallization layers that can be redesigned and deposited during a production run without redesigning the semiconductor layers of the device. The depositing of the mask can be performed by vapor deposition of aluminum or other metals using techniques well known in the art. The mask connects devices within an interconnect array or “plane” comprising two sets of conductors, a set of logic inputs and a set of logic gate inputs. The sets of conductors are coupled together with devices that create a logic contribution from the logic inputs to the logic gate inputs. Fuse PLAs allow programming of the device after manufacture by using a programming unit or appropriate in-circuit electronics to allow programming of the device.
PLAs have found use in complex logic network implementations and recently in high-speed microprocessor core designs where they can be used to implement the state machines and control logic of the processor. A disadvantage associated with the use of PLAs is associated with the organization of their logic. Due to the sum-of-products or product-of-sums arrangement, implementation of complex logic functions may not be efficient. An input might only be used in a very limited sense, for example within only one midterm in the entire logic array. The number of maxterms may be limited in the interconnect between the input plane and the output plane, making some logic equation implementations too complex for a particular PLA. These limitations are usually overcome by adding additional static or dynamic gates to implement the additional logic required, but this arrangement is non-programmable and loses the benefits of quick mask turn-around and the structured design available with programmable logic.
Therefore, it would be desirable to implement programmable logic in such a way as to improve the efficiency of logic implementations and additionally, to facilitate the use of PLAs in logic designs.
SUMMARY OF THE INVENTION
The objectives of improving the efficiency of programmable logic and facilitating the use of PLAs in logic designs are accomplished in dynamic programmable logic gate having a pre-charge device for charging a summing node and a cell matrix coupled to the summing node for receiving multiple logic inputs. The cell matrix has rows and columns for accepting cells selected that hold either a conductor or a transistor. The transistors connected in the matrix are coupled to one of the logic inputs. The transistor and conductor cells are designed so that they may couple to a next lower cell within the matrix, and optionally to the a next lower cell in an adjacent column. The objectives are also achieved in methods for fabricating and operating the dynamic programmable logic gate described above.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5471154 (1995-11-01), Gordon et al.
patent: 5670898 (1997-09-01), Fang
Dhong Sang Hoo
Ngo Hung Cai
Park Jae-hong
Takahashi Osamu
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Le Don Phu
Salys Casimer K.
Tokar Michael
LandOfFree
Method and apparatus for implementing logic using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for implementing logic using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for implementing logic using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2459054