Method and apparatus for implementing fault tolerant phase...

Details Method and apparatus for implementing fault tolerant phase... Method and apparatus for implementing fault tolerant phase...

2007-08-21

2007-08-21

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S376000

Reexamination Certificate

active

11186595

ABSTRACT:
A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. The voter circuit provides an output feedback frequency signal based upon a majority vote of the sub-divide by N functions.

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patent: 2003/0056170 (2003-03-01), Majumdar

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