Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2007-09-26
2011-11-01
Garbowski, Leigh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S106000
Reexamination Certificate
active
08051402
ABSTRACT:
Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system are described. In one example, transactors and communication channels are identified in a hierarchy of the test bench. Software side endpoints of the communication channels are automatically bound to hardware side endpoints of the communication channels during verification based on naming attributes of the transactors and communication channels with respect to the software side and the hardware side of the test bench.
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patent: 7260798 (2007-08-01), Gupta et al.
patent: 7440885 (2008-10-01), Garcia et al.
Accellera, “Standard Co-Emulation Modeling Interface (SCE-MI) Reference Manual,” Version 1.1.0, Jan. 13, 2005, 134 pages.
Kim et al., “Reducing Transaction-Level Modeling Effort while Retaiming Low Communication Overhead for HW/SW Co-Emulation System,” Int'l Symposium on VLSI Design, Automation and Test, Apr. 25-27, 2007, pp. 1-4.
Cadence Design Systems Inc.
Colandreo, Esq. Brian J.
Garbowski Leigh
Holland & Knight LLP
Whittenberger, Esq. Mark H.
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