Method and apparatus for implementing chip-to-chip...

Details Method and apparatus for implementing chip-to-chip... Method and apparatus for implementing chip-to-chip...

2005-04-12

2005-04-12

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S100000, C710S305000

Reexamination Certificate

active

06880026

ABSTRACT:
A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized. Once link synchronization is established, the source transmits configuration information to the destination using normal bus messages. Programmable delay elements and configuration registers are set.

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U.S. Appl. No. 10/147,682, filed May 16, 2002, “Method and Apparatus for Implementing Multiple Configurable Sub-Busses of a Point-to-Point Bus”.

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