Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2008-01-15
2009-06-23
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S038000, C326S040000
Reexamination Certificate
active
07551002
ABSTRACT:
A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.
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Reuland Paul Gary
Schuelke Brian Andrew
International Business Machines - Corporation
Le Don P
Pennington Joan
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