Method and apparatus for implementing atomicity of memory...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S225000, C711S152000, C710S200000

Reexamination Certificate

active

09592106

ABSTRACT:
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.

REFERENCES:
patent: 4197579 (1980-04-01), Otis, Jr. et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 5142676 (1992-08-01), Fried et al.
patent: 5309173 (1994-05-01), Izzi et al.
patent: 5321823 (1994-06-01), Grundmann et al.
patent: 5361337 (1994-11-01), Okin
patent: 5461722 (1995-10-01), Goto
patent: 5511210 (1996-04-01), Nishikawa et al.
patent: 5535365 (1996-07-01), Barriuso et al.
patent: 5542088 (1996-07-01), Jennings, Jr. et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5600837 (1997-02-01), Artieri
patent: 5604877 (1997-02-01), Hoyt et al.
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5649144 (1997-07-01), Gostin et al.
patent: 5694572 (1997-12-01), Ryan
patent: 5701432 (1997-12-01), Wong et al.
patent: 5713038 (1998-01-01), Motomura
patent: 5745778 (1998-04-01), Alfieri
patent: 5748468 (1998-05-01), Notenboom et al.
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5784613 (1998-07-01), Tamirisa
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5815733 (1998-09-01), Anderson et al.
patent: 5852726 (1998-12-01), Lin et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5867725 (1999-02-01), Fung et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5933627 (1999-08-01), Parady
patent: 5946711 (1999-08-01), Donnelly
patent: 5987492 (1999-11-01), Yue
patent: 6016542 (2000-01-01), Gottlieb et al.
patent: 6018759 (2000-01-01), Doing et al.
patent: 6029228 (2000-02-01), Cai et al.
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6115802 (2000-09-01), Tock et al.
patent: 6119203 (2000-09-01), Snyder et al.
patent: 6192384 (2001-02-01), Dally et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6260077 (2001-07-01), Rangarajan et al.
patent: 6308261 (2001-10-01), Morris et al.
patent: 6356996 (2002-03-01), Adams
patent: 6430593 (2002-08-01), Lindsley
patent: 6442675 (2002-08-01), Derrick et al.
patent: 6487571 (2002-11-01), Voldman
patent: 6493749 (2002-12-01), Paxhia et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 2002/0062435 (2002-05-01), Nemirovsky et al.
patent: 2003/0084269 (2003-05-01), Drysdale et al.
patent: 0806730 (1997-11-01), None
patent: 0827071 (1998-03-01), None
patent: 0953903 (1999-11-01), None
patent: 2103630 (1988-10-01), None
patent: 63254530 (1988-10-01), None
patent: 4335431 (1992-11-01), None
patent: 546379 (1993-02-01), None
patent: 09506752 (1997-06-01), None
patent: 1011301 (1998-01-01), None
patent: 10124316 (1998-05-01), None
patent: 10207717 (1998-08-01), None
patent: WO9427216 (1994-11-01), None
patent: WO0023891 (2000-04-01), None
Pai et al. An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors pp. 12-23, Oct. 1996.
Grunewald et al. Toward Extremely Fast Context Switching in a Block-Multithreaded Processor 592-599, 1996.
Bradford et al. Efficient Synchronization for Multithreaded Processors pp. 1-14, Jan. 1998.
Tullsen et al. Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, Jun. 1998,
Tullsen et al., Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, 1999, pp. 1-5, especially pp. 2-4.
Fiske et al., “Thread Prioritization: A Thread Schedluling Mechanism for Multiple-Context Parallel Processors”, 1995, pp. 210-221, IEEE.
Yamamoto, Wayne, “An Analysis of Multistreamed, Superscalar Processor Architectures”, University of California Santa Barbara dissertation, Dec. 1995, Santa Barbara, US.
Steere et al., “A Feedback—Driven Proportion Allocator for Real-Rate Scheduling”, Third Symposium on Operating Systems Design and Implementation, Feb. 1999, pp. 145-458, USENIX Association.
Yamamoto et al., “Increasing Superscalar Performance Through Multistreaming”, 1995.
Tullsen et al., “Simultaneous Multithreading: Maximizing on-Chip Parallelism”, 22nd Annual International Symposium on Computer Architecture, Jun. 1995, Santa Margherita Ligure, Italy.
Yoaz et al., “Speculation Techniques for Improving Load Related Instruction Scheduling”, 1999, pp. 42-53, IEEE.
Kessler, R.E., “The Alpha 21264 Microprocessor: Out-of-Order Execution at 600 Mhz”, Aug. 1998.
Yamamoto et al., Performance Estimation of Multistreamed, Superscalar Processors, IEEE. 1994, pp. 195-204, Hawaii, US.
Nemirovsky et al., “Quantitative Study of Data Caches on a Multistreamed Architecture”, Workshop on Multithreaded Execution Architecture and Compilation, Jan. 1998.
Li et al., “Design and Implementation of a Multiple-Instruction-Stream Multiple-Execution-Pipeline Architecture”, 7th International Conference on Parallel and Distributed Computing and Systems, Oct. 1995, Washington, D.C.
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, May 1994, pp. 70-72, Morgan Kaufmann, San Francisco.
MC68020 32-Bit Microprocessor User's Manual, Third Edition, 1989, pp. 3-125, 3-126, and 3-127, Prentice Hall, New Jersey.
Potel, M.J., Real-Time Playback in Animation Systems, Proceedings of the 4th Annual Conference on Computer Graphics and Interactive Techniques. 1977, pp. 72-77, San Jose, CA.
Arm Architecture Reference Manual, 1996, pp. 3-41, 3-42, 3-43, 3-67, 3-68, Prentice Hall.
ESA/390 Principles of Operation, IBM Library Server, 1993, Table of Contents and Para. 7.5.31 and 7.5.70 (available at :http://publibz.boulder.ibm.com/cgi-bin/bookmgr—OS390/BOOK/DZ9AR001/CCONTENTS).
MC88110 Second Generation RISC Microprocessor User's Manual, 1991, pp. 10-66, 10-67 and 10-71, Motorola, Inc.
Diffendorff, Keith et al., Organization of the Motorola 88110 Superscalar RISC Microprocessor, IEEE Micro, Apr. 1992, pp. 40-63, vol. 12, No. 2.
Kane, Gerry, PA-RISC 2.0 Architecture, 1996, pp. 7-106 and 7-107, Prentice Hall, New Jersey.
Diffendorf, Keith et al., AltiVec Extension to PowerPC Accelerates Media Processing, Mar.-Apr. 2000, pp. 85-95, IEEE Micro, vol. 20, No. 2.
Nemirovsky et al., DISC: Dynamic Instruction Stream Computer, ACM, 1991, pp. 163-171.
Donalson et al., “DISC: Dynamic Instruction Stream Computer, An Evaluation of Performance”, 26th Hawaii Conference on Systems Sciences, 1993, pp. 448-456, vol. 1.
Grunewald, Winfried et al., Towards Extremely Fast Context Switching in a Block-Multthreaded Processor, Proceedings of EUROMICRO-22, 1996, pp. 592-599.
Bradford, Jeffrey et al., Efficient Synchronization for Multithreaded Processors, Workshop on Multithreaded Execution, Architecture and Compilation, Jan.-Feb. 1998, pp. 1-4.
Tullsen, Dean et al., Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, UCSD CSE Technical Report CS98-587, Jun. 1998, all pages, US.
Diffendorff, Keith, “WinChip 4 Thumbs Nose at ILP,”Microprocessor Report, vol. 12, No. 16, 10 pages (Dec. 7, 1998).
Eggers et al. “Simultaneous Multithreading: A Platform for Next-Generation Processors”, IEEE Micro, 1997.
Diffendorff, Keith; “Jalapeno Powers Cyrix's M3”, Microprocessor Report, Vo. 12, No. 15, Nov. 16, 1998.
Becker et al; “The PowerPC 601 Microprocessor”, IEEE Micro,

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for implementing atomicity of memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for implementing atomicity of memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for implementing atomicity of memory... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3855202

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.