Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1997-02-06
1998-11-24
Santamauro, Jon
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 83, 326 87, H03K 1900, H03K 190175
Patent
active
058412999
ABSTRACT:
A low power-dissipation gate for use in a logic cascade is described. The gate includes a pull-up switch arrangement, a pull-down switch arrangement and hold circuitry for holding an output of the gate while it is evaluated by a downstream gate. The gate is coupled between a pair of power rails which carry power clock waveforms which are approximately 180 degrees out-of-phase with each other. The gate is also coupled to receive a logic input signal, and a logic complement input signal. The transitions of the logic complement input signal are delayed by a pre-determined amount relative to transitions of the logic input signal. Each of the pull-up and pull-down switch arrangements have both P-type and N-type switching devices, and are distinguished in that the P-type switching devices of the pull-up switch arrangement are coupled to receive the input signal, while the P-type switching devices of the pull-down switch arrangement are coupled to receive the input complement signal. Similarly, the N-type switching devices of the pull-up switch arrangement are coupled to receive the input complement signal, while the N-type switching devices of the pull-down switch arrangement are coupled to receive the input signal.
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Intel Corporation
Le Don Phu
Santamauro Jon
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