Method and apparatus for implementing a single cycle...

Details Method and apparatus for implementing a single cycle... Method and apparatus for implementing a single cycle...

2005-01-25

2005-01-25

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C708S207000

Reexamination Certificate

active

06848074

ABSTRACT:
An improved method and apparatus for performing single-cycle operations (such as Viterbi decode) in digital processors is disclosed. In one aspect, the invention comprises methods for storing (“packing”) old and new metric data in memory that cooperate with a single-operand instruction adapted to perform single cycle calculations such as the Viterbi butterfly. Accordingly, such calculations can be computed effectively in software in a single cycle. In another aspect, an improved memory addressing mode is used to write back two new output results at the completion of instruction execution. The improved packing of state metrics in memory, single-operand instruction, and addressing mode can advantageously be integrated into any processor (e.g., DSP, RISC-DSP, or configurable processor) with appropriate memory. The user of such a processor may accordingly write software using the single-operand instruction to perform Viterbi decode with the efficiency comparable to a dedicated hardware implementation.

REFERENCES:
patent: 4979175 (1990-12-01), Porter
patent: 5068859 (1991-11-01), Collins et al.
patent: 5197130 (1993-03-01), Chen et al.
patent: 5220570 (1993-06-01), Lou et al.
patent: 5309494 (1994-05-01), Grehl
patent: 5327440 (1994-07-01), Fredrickson et al.
patent: 5331664 (1994-07-01), Desperben et al.
patent: 5408502 (1995-04-01), How
patent: 5412669 (1995-05-01), Foland, Jr.
patent: 5430744 (1995-07-01), Fettweis et al.
patent: 5469452 (1995-11-01), Zehavi
patent: 5537424 (1996-07-01), Karabed et al.
patent: 5633897 (1997-05-01), Fettweis et al.
patent: 5710784 (1998-01-01), Kindred et al.
patent: 5715470 (1998-02-01), Asano et al.
patent: 5742621 (1998-04-01), Amon et al.
patent: 5748515 (1998-05-01), Glass et al.
patent: 5752001 (1998-05-01), Dulong
patent: 5778241 (1998-07-01), Bindloss et al.
patent: 5781569 (1998-07-01), Fossorier et al.
patent: 5784602 (1998-07-01), Glass et al.
patent: 5794062 (1998-08-01), Baxter
patent: 5796757 (1998-08-01), Czaja
patent: 5815515 (1998-09-01), Dabiri
patent: 5867408 (1999-02-01), Chauvel et al.
patent: 5881257 (1999-03-01), Glass et al.
patent: 5881259 (1999-03-01), Glass et al.
patent: 5881263 (1999-03-01), York et al.
patent: 5896521 (1999-04-01), Shackleford et al.
patent: 5912908 (1999-06-01), Cesari et al.
patent: 5987490 (1999-11-01), Alidina et al.
patent: 5987638 (1999-11-01), Yu et al.
patent: 5991785 (1999-11-01), Alidina et al.
patent: 6002881 (1999-12-01), York et al.
patent: 6009128 (1999-12-01), Mobin et al.
patent: 6029267 (2000-02-01), Simanapalli et al.
patent: 6070263 (2000-05-01), Tsui et al.
patent: 6115436 (2000-09-01), Ramesh et al.
patent: 6125153 (2000-09-01), Sugisawa et al.
patent: 6148431 (2000-11-01), Lee et al.
patent: 6163581 (2000-12-01), Kang
patent: 6259749 (2001-07-01), Andoh
patent: 6272188 (2001-08-01), Mobin et al.
patent: 6289487 (2001-09-01), Hessel et al.
patent: 6313963 (2001-11-01), Hsieh
patent: 6317472 (2001-11-01), Choi et al.
patent: 6330684 (2001-12-01), Yamanaka et al.
patent: 6385757 (2002-05-01), Gupta et al.
patent: 6397240 (2002-05-01), Fernando et al.
patent: 6401190 (2002-06-01), Nishioka et al.
patent: 6425116 (2002-07-01), Duboc et al.
patent: 6442672 (2002-08-01), Ganapathy
patent: 6446193 (2002-09-01), Alidina et al.
patent: 6457173 (2002-09-01), Gupta et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6477697 (2002-11-01), Killian et al.
patent: 6594752 (2003-07-01), Baxter
patent: 6701515 (2004-03-01), Wilson et al.
patent: 20010001616 (2001-05-01), Rakib et al.
patent: 20010004391 (2001-06-01), Naitou
patent: 20010007142 (2001-07-01), Hocevar et al.
patent: 20010021153 (2001-09-01), Taguchi et al.
patent: 20010024474 (2001-09-01), Rakib et al.
patent: 20010033611 (2001-10-01), Grimwood et al.
patent: 20010033626 (2001-10-01), Symes et al.
patent: 20010037486 (2001-11-01), Traeber
patent: 20010040916 (2001-11-01), Sato
patent: 1 111 801 (2001-06-01), None
patent: 1 120 916 (2001-08-01), None
patent: WO 0167619 (2001-09-01), None
Ovadia, et al., “PalmDSPCore™—Dual MAC and Parallel Modular Architecture,” (Date Unknown), consisting of 8 pages.
Hardin, et al., “Accelerating Viterbi Decoer Simulations,” (Jan., 1999), CommsDesign, consisting of 9 pages.
Shah, et al., “Viterbi Project Final Report,” (Spring, 1999), consisting of 15 pages.

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