Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2007-06-19
2007-06-19
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S216000, C707S793000
Reexamination Certificate
active
10735107
ABSTRACT:
A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs and multiplexers for receiving hash function outputs, and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.
REFERENCES:
patent: 5530834 (1996-06-01), Colloff et al.
patent: 6223172 (2001-04-01), Hunter et al.
patent: 7002965 (2006-02-01), Cheriton
Kao Sophia W.
Malalur Govind
Yang Brian Hang Wai
Peugh Brian R.
Raza Microelectronics Inc.
Rutz Jared
Stevens Law Group
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