Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-12-31
2002-07-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C326S086000, C326S090000, C361S760000
Reexamination Certificate
active
06417688
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to integrated circuit and printed circuit board design and manufacture and more specifically to design and manufacture of integrated circuits and printed circuit boards in which a large number of loads on a bus must be driven.
2. Description of the Related Art
Printed circuit boards have long contained buses or conductors that could be driven by more than one driver at a time. Likewise, these buses were also often connected to multiple receivers. With relatively small printed circuit boards and/or relatively low frequency signals, these buses did not cause significant delays and noise created by multiple reflections on these buses did not present too much trouble. However, as processing speeds requiring higher bandwidth delays caused by and noise generated by reflections on multi-load buses and other connections on printed circuit boards assume an increasing importance.
Previously, a method for creating a five load bus that can handle moderate signaling rate of newer integrated circuits has been available. At higher rates, it is essential to reduce reflections and get the bus to settle down quickly. The best known topology of buses was suitable for connection directly to only four loads. In prior art systems, such a four load bus was useful as there were often only two or three devices which would drive a bus or receive signals from a bus. Five load systems are useful in current system configurations, consisting primarily of four processor agents and one node controller chip. The previous four load topology cannot be directly scaled to this five load configuration. At the same time, accesses by the processors or memory management device to the bus must be fast enough to satisfy the demands of the processors for data input/output functions.
Illustrated in
FIG. 1A
is a common prior art bus topology as applied to a five load bus. Driver/receiver
10
is coupled to stub
15
which in turn is coupled to bus
60
. Driver/receiver
20
is coupled to stub
25
which in turn is coupled to bus
60
. Similarly, driver/receiver
30
is coupled to stub
35
which is coupled to bus
60
, driver/receiver
40
is coupled to stub
45
which is coupled to bus
60
, and driver/receiver
50
is coupled to stub
55
which is coupled to bus
60
. Bus
60
is terminated at one end by termination resistor
70
and power supply
75
, and bus
60
is terminated at the other end by termination resistor
80
and power supply
85
.
As is illustrated, driver/receiver
10
drives the bus, and causes a reflection on stub
15
. The signal propagates through the bus, and reflections are also observed on stubs
25
,
35
,
45
, and
55
. These reflections appear as noise to the main signal on the bus and increase the settling time required between driving distinct signals on the bus. Ultimately, this noise limits the maximum frequency which may be achieved with this bus.
SUMMARY OF THE INVENTION
In one embodiment, the invention is a method of forming a bus. A first conductor having a first impedance is provided, the first conductor is routed through a fifth chip. Coupling of the first conductor to a first chip with a first termination impedance occurs. Coupling of the first conductor to a second chip with a second termination impedance occurs. Coupling of the first conductor to a third chip with a third termination impedance occurs, and coupling of the first conductor to a fourth chip with a fourth termination impedance occurs.
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patent: 5528168 (1996-06-01), Kleveland
patent: 5638402 (1997-06-01), Osaka et al.
patent: 5982192 (1999-11-01), Saito
patent: 6097208 (2000-08-01), Okajima et al.
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patent: 6232792 (2001-05-01), Starr
patent: 6239619 (2001-05-01), Yuan et al.
Dabral Sanjay
Zeng Ming
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Park Steven S.
Tokar Michael
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