Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1997-08-08
1999-11-16
Santamauro, Jon
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 97, 326121, H03K 1996
Patent
active
059864761
ABSTRACT:
A gate for use in a logic cascade is described. The gate comprises two evaluate and precharge network pairings. One of the evaluate networks generates an output signal, while the other evaluate network generates an output complement signal. Each of the evaluate networks further has a precharge network associated therewith. Each of the evaluate and precharge networks is coupled to a common power rail, which carries a power clock signal, so as to provide an approximately constant capacitive load to a power clock signal generation circuit. Each of the evaluate networks further includes a principle MOSFET switch and a complementary MOSFET switch, the complimentary MOSFET switch having a threshold voltage different from that of the principle MOSFET switch.
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Intel Corporation
Santamauro Jon
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