Method and apparatus for implementing a branch target buffer cac

Details Method and apparatus for implementing a branch target buffer cac Method and apparatus for implementing a branch target buffer cac

1996-06-18

1998-11-24

Kim, Kenneth S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395382, 395584, 395586, 711 5, G06F 938

Patent

active

058420088

ABSTRACT:
A Branch Target Buffer Circuit in a computer processor that predicts branch instructions within a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache with multiple BTB banks that store branch information about previously executed branch instructions. The branch information stored in each bank of the Branch Target Buffer Cache is addressed by the last byte of each branch instruction When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache banks to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an instruction Fetch Unit about the upcoming branch instruction.

REFERENCES:
patent: 4943908 (1990-07-01), Emma et al.
patent: 5434985 (1995-07-01), Emma et al.
patent: 5530825 (1996-06-01), Black et al.
patent: 5706492 (1998-01-01), Hoyt et al.

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