Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-02-14
2006-02-14
Le, Don (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C326S082000
Reexamination Certificate
active
06998870
ABSTRACT:
A method and apparatus for impedance matching in systems configured for multiple processors is disclosed. In one embodiment, a computer system includes a first processor socket and a second processor socket, each configured to accommodate a processor. The processor sockets may be electrically coupled to each other. A first I/O node may be electrically coupled to the first processor socket and a second I/O node may be electrically coupled to the second processor socket. A processor may be mounted in the first processor socket, while an impedance matching circuit may be mounted in the second processor socket. The impedance matching circuit may electrically couple the processor mounted in the first processor socket to the second I/O node, thereby allowing the computer system to utilize the I/O capability provided by the second I/O node even when a second processor is not present in the system.
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Dowling Jonathan P.
Gulick Dale E.
Advanced Micro Devices , Inc.
Heter Erick A.
Kivlin B. Noäl
Le Don
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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