Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
1998-08-31
2003-06-03
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S701000
Reexamination Certificate
active
06574756
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to data storage devices, and more particularly to a method and apparatus for identifying the start of a data field using a fault tolerant sync word.
2. Description of Related Art
Memory systems, optical or magnetic, have moving recording media on which information is recorded in sections or sectors. These information sections must be accessible so that desired information can be read therefrom. Accessibility is achieved by providing header sections of discrete recordings on the moving media ahead of these information sections, defining fields of bit code patterns, forming synchronizing fields, start of information or word sync fields, together with data address fields, which together contain information for providing timed access to the recorded information or data.
The fields described above include recordings on the media in the form of bits, such as magnetic bits on magnetic media, which are transduced as the media moves past a transducer disposed adjacent the surface of the media. The transducer is optically or magnetically coupled to the recorded bits on the media. The bits on the magnetic media are serially recorded in patterns of transition and non-transition magnetic dibits or optically readable bits. The media surface is usually of one state of polarization, which when read within the clock pulse intervals provides indications which characterize the non-transition bits. Transition bits are oppositely poled from the non-transition bits in the magnetic media and therefore provide different indications.
The header section in the form of bit patterns, may be used for various purposes. Among such purposes is the synchronization and phase locking the servo system and providing read/write controls with respect to the media for reading and writing operations, and to provide an indication useful in identifying a particular location or position on a moving media at which information is to be recorded or read by the transducer. The start of the sync field is part of the header field. The header filed may also include a word sync field for identifying the first bit in the data field.
It is difficult in high density recording to write codes without error. Without defect tolerance in reading such codes, such as a word sync code, it is necessary to spare (skip over) any section or sector that contains a defect in the word sync field. This is wasteful of data space. Also, a partial—response maximum—likelihood (PRML) detection channel is often used to achieve high data density in writing and reading digital data on recording media. However, uncoded binary data is not suitable for PRML data channels because unconstrained customer data may contain long spans of null signal or adjacent zeroes which provide no timing or gain information to the channel and prevent proper timing and gain tracking to the readback signal waveform. Rate 8/9 modulation codes are known for use with PRML detection channels to assure a minimum correction rate for PRML timing and gain control loops. Further, as compared with 8/9 coding, the use of 16/17 rate coding allows customer data to be stored on the disk more efficiently. Only 17 bits need to be stored on the disk for every 16 bits of customer data. However, current word sync fields for identifying the start of a data field do not provide sufficient fault tolerance with 16/17 rate coding.
It can be seen that there is a need for a method and apparatus for identifying the start of a data field using a fault tolerant sync word with 16/17 rate coding.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for identifying the start of a data field using a fault tolerant sync word with 16/17 rate coding.
The present invention solves the above-described problems by providing a word sync field that uses a 16/17 byte pattern that is repeated. The format of the word sync allows the proper identification of the start of the data even if only certain portions of the word sync are recovered.
An encoded data block in accordance with the principles of the present invention includes a sync field for providing proper timing for bit synchronization and a word sync field following the sync field, the word sync field being written with a predetermined phase relative to the sync field to identify a start of a data field.
Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that the word sync field comprises N word sync patterns, each word sync pattern comprising two subpatterns, wherein the phase relationship of the word sync field and the sync field enables identification of the start of the data field by identifying any N subpatterns.
Another aspect of the present invention is that each of the N word sync patterns comprises a 17 bit word sync pattern, the 17 bit word sync patterns comprising an 8 of 9 byte and an 8 of 8 byte.
Another aspect of the present invention is that the N word sync patterns further comprises three word sync patterns forming six subpatterns, wherein only three of the six subpatterns must be detected to identify the start of the data field.
Another aspect of the present invention is that the N word sync patterns further comprises two word sync patterns forming four subpatterns, wherein only two of the four subpatterns must be detected to identify the start of the data field.
Another aspect of the present invention is that the N word sync patterns further comprises one word sync pattern forming two subpatterns, wherein only one of the two subpatterns must be detected to identify the start of the data field.
Another aspect of the present invention is that the sync field comprises a modulus
2
phase and the word sync comprises a modulus
17
phase.
Another aspect of the present invention is that the word sync field is written without one length magnets.
Another aspect of the present invention is that the data field follows the word sync field.
Another aspect of the present invention is that the word sync field comprises a 16/17 byte pattern, the 16/17 byte pattern further comprising an 8/9 subpattern and an 8/8 subpattern and being repeated N times, wherein the start of the data field is identified when a pattern match for any N of the subpatterns is identified.
Another aspect of the present invention is that a start of data field detector is provided with includes a bit sync detector for providing a modulus
2
phase and a word sync detector, coupled to the bit sync detector, the word sync detector counting the modulus
2
phase and a modulus
17
phase count N derived from a word sync pattern, comparing the modulus
2
phase count to the modulus
17
phase count, detecting when the modulus
2
phase count and the modulus
17
phase count N occur simultaneously, identifying the start of the data field relative to the word sync pattern last incrementing the modulus
17
count.
Another aspect of the present invention is that a start of data field detector is provided that includes a bit sync detector for detecting a sync field and providing a modulus M phase signal in response thereto and a word sync detector, coupled to the bit sync detector, for detecting word sync patterns written with a predetermined phase relative to the sync field, wherein the word sync detector further includes a modulus J phase signal counter for receiving the modulus J phase signal and locking thereto, a register ring, the register ring comprising K registers, one of the K registers being incremented when a pattern match is detected to produce a modulus K signal, a multiplexer, coupled to the register ring and the modulus J phase signal counter, the multiplexer being modulated by the modulus J phase signal for representing the phase of the sync field and a greater than
Galbraith Richard L.
Walker Gary W.
Chung Phung M.
Hollingsworth Mark A.
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