Method and apparatus for identifying redundant scan elements

Details Method and apparatus for identifying redundant scan elements Method and apparatus for identifying redundant scan elements

2011-03-01

2011-03-01

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C714S724000, C714S726000, C714S727000, C714S729000

Reexamination Certificate

active

07900163

ABSTRACT:
An approach for producing optimized integrated circuit designs that support sequential flow partial scan testing may be embedded within an integrated circuit electronic design device. Using the approach, an integrated circuit design may be analyzed to identify and remove scan-enabled memory elements, or scan elements, that are redundant. The redundant scan elements may be replaced with memory elements that do not support scan testing. Once the redundant scan elements are removed, the integrated circuit design my be optimized using automated techniques to reduce the area of the integrated circuit physical layout and to simplify/minimize routing connections between remaining features within the integrated circuit design. The described approach may achieve a reduced total area layout and complexity, an improved time/frequency response, and/or reduced power consumption and/or heat generation within the circuit design, without reducing the fault coverage achieve during testing.

REFERENCES:
patent: 6067650 (2000-05-01), Beausang et al.
patent: 6463561 (2002-10-01), Bhawmik et al.
patent: 6651197 (2003-11-01), Wildes et al.
patent: 2007/0260949 (2007-11-01), Fredrickson et al.

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