Method and apparatus for identifying line-end features for...

Details Method and apparatus for identifying line-end features for... Method and apparatus for identifying line-end features for...

2007-03-20

2007-03-20

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10845566

ABSTRACT:
One embodiment of the invention provides a system that facilitates identifying line-end features in a layout for an integrated circuit. The system operates by first receiving the layout for the integrated circuit. Next, the system selects a polygon from the layout and marks a line-end seed on the polygon. The system then determines if the line-end seed is associated with a line feature, and if so, the system marks the line-end feature inside the line feature.

REFERENCES:
patent: 6670081 (2003-12-01), Laidig et al.
patent: 7005218 (2006-02-01), Zhang
Balasinski et al., “Comparsion of Mask Writing Tools and Mask Simulations for 0.16um Devices,” IEEE, Sep. 1999, pp. 372-377.
Strojwas et al., “Layout Manufacturability Analysis Using Regorous 3-D Topolography Simulation,” IEEE, Oct. 2001, pp. 263-266.
Balasinski et al., “A Novel Approach to Simulate the Effect of Optical Proximity on MOSFET Parametric Yield,” IEDM, 1999, pp. 37-6.1-37.6.4.

Affiliated with

Also associated with

Rating

Method and apparatus for identifying line-end features for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for identifying line-end features for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for identifying line-end features for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3758616