Patent
1995-12-22
1998-06-16
Treat, William M.
39580023, G06F 900, G06F 928
Patent
active
057685568
ABSTRACT:
An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set. The second instruction is subsequent in the succession to the first instruction. The first register storage set is a first storage locus for storing a target operand of the first instruction; the second register storage set is a second storage locus for storing a source operand for the second instruction. The logical treating effects the identifying of dependencies between the target operand and the source operand.
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Canada Miles Gaylord
Esling Walter
Heaslip Jay Gerald
Hesson James
Mahin Stephen William
International Business Machines - Corporation
Murray Susan M.
Treat William M.
Winder Patrice L.
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