Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-11
2009-02-24
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000, C430S030000
Reexamination Certificate
active
07496883
ABSTRACT:
One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout such that the PSM-layout is phase-assignable if and only if the phase-conflict graph is bipartite. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. The system can also be used to correct a given set of phase conflicts in a PSM-layout.
REFERENCES:
patent: 6698007 (2004-02-01), Wu et al.
patent: 6832364 (2004-12-01), Heng et al.
patent: 7216331 (2007-05-01), Wu et al.
patent: 2002/0083410 (2002-06-01), Wu et al.
Chiang Charles C.
Sinha Subarnarekha
Do Thuan
Doan Nghia M
Park Vaughan & Fleming LLP
Synopsys Inc.
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