Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-15
2004-09-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S005000, C378S035000
Reexamination Certificate
active
06795955
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for using a suggested solution to speed up an iterative process, such as optical proximity correction, for simulating and correcting a layout on a semiconductor chip.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term “mask” as used in this specification is meant to include the term “reticle.”) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some other type of electromagnetic radiation together with suitably adapted masks and lithography equipment.
This light is reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem that arises during the optical lithography process is “line end shortening” and “pullback”. For example, the upper portion of
FIG. 1
illustrates a design of a transistor with a polysilicon line
102
, running from left to right, that forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. The lower portion of
FIG. 1
illustrates a printed image that results from the design. Note that polysilicon line
102
has been narrowed using optical phase shifting in order to improve the performance of the transistor by reducing the resistance through the gate region.
Also note that because of optical effects and resist pullback there is a significant amount of line end shortening. This line end shortening is due to optical effects that cause the light to expose more of the resist under a line end than under other portions of the line.
In order to compensate for line end shortening, designers often add additional features, such as “hammer heads,” onto line ends (see top portion of FIG.
2
). The upper portion of
FIG. 2
illustrates a transistor with a polysilicon line
202
, running from left to right, which forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. A hammer head
204
is included on the end of polysilicon line
202
to compensate for the line end shortening. As is illustrated in the bottom portion of
FIG. 2
, these additional features can effectively compensate for line end shortening in some situations.
These additional features are typically added to a layout automatically during a process known as optical proximity correction (OPC). For example,
FIG. 3
illustrates line end geometry
302
(solid line) prior to OPC and the resulting corrected line end geometry
304
after OPC (dashed line). Note that the corrected line end geometry
304
includes regions with a positive edge bias in which the size of the original geometry
302
is increased, as well as regions of negative edge bias in which the size of the original geometry
302
is decreased.
Performing an operation, such as OPC, can be extremely time-consuming, because the operation typically involves numerous iterations of a time-consuming modeling and correction process. Furthermore, the operation must be applied to all of the cells that comprise a layout of an integrated circuit.
In order to speed up operations such as OPC, existing systems often perform hierarchical processing on a layout to identify identical cells that have the same surrounding environment. (Within this specification and the associated claims, the term “cell” refers to a unit of design, such as an arbitrary geometric region or potion of the layout.) If such identical instances of cells are identified, the existing systems can use a solution computed for one cell as a solution for all other identical instances of the cell. This saves a great deal of time for layouts that contain many instances of the same cell.
Unfortunately, existing systems cannot reuse solutions in cases where identical cells have different surrounding environments, or when a layout of a given cell differs only slightly from the layout of another cell.
Moreover, existing systems do a poor job of distributing the workload involved in computing solutions for cells across multiple processing nodes that are typically available in high-performance computing systems.
What is needed is a method and an apparatus that reuses a solution for a given cell in computing a solution for a cell with a different environment and/or a slightly different layout.
SUMMARY
One embodiment of the invention provides a system for speeding up an iterative process that simulates and corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial input to the iterative process that produces the solution for the target cell.
In a variation on this embodiment, the target cell is similar to the preceding cell if the layout of the target cell matches the layout of the preceding cell but the environment surrounding the target cell differs from the environment surrounding the preceding cell.
In a variation on this embodiment, if the previously calculated solution for the preceding cell is used as the initial input to the iterative process, the iterative process only operates on features within a border region located just inside the outside edge of the target cell that can be affected by the environment surrounding the target cell, and ignores features within the target cell that are not located within the border region.
In a variation on this embodiment, the target cell is similar to the preceding cell if the layout of the target cell differs from the layout of the preceding cell by less than a pre-specified amount. For example, in one embodiment of the present invention, the target cell is similar to the preceding cell if a specific percentage (say 95%) of the layout of the target cell is identical to the layout of the preceding cell.
In a variation on this embodiment, if the previously calculated solution for the preceding cell is used as the initial input for the iterative process, and if the iterative process produces a simulation result that differs significantly from the desired layout, the system restarts the iterative process using the desired layout instead of the previously calculated solution as the initial input to the iterative process.
In a variation on this embodiment, while performing the iterative process the system repeatedly simulates a current solution for the target cell to produce a current simulated layout. If the current manufactured result as determined by simulation (or “simulated layout”) differs from the desired layout by less than a pre-specified amou
MacLean Kevin D.
Sturgeon Roger W.
Kik Phallaka
Numerical Technologies
Park Vaughan & Fleming LLP
Smith Matthew
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