Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-15
2008-01-15
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000, C430S030000
Reexamination Certificate
active
07320119
ABSTRACT:
One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which can be used to detect edges in an image. Next, the system identifies a problem edge in the mask layout using the edge-detecting process-sensitivity model.
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Melvin, III Lawrence S.
Painter Benjamin D.
Shiely James P.
Yan Qiliang
Chiang Jack
Doan Nghia M.
Park Vaughan & Fleming LLP
Synopsys Inc.
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