Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-10
2007-07-10
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11083656
ABSTRACT:
One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes a gradient-magnitude of the process-sensitivity model. Next, the system identifies a problem area in the mask layout using the gradient-magnitude of the process-sensitivity model. Identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout.
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Melvin, III Lawrence S.
Shiely James P.
Yan Qiliang
Chiang Jack
Doan Nghia M.
Park Vaughan & Fleming LLP
Synopsys Inc.
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