Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-31
2007-07-31
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11065409
ABSTRACT:
One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then identifies a problem area in the mask layout using the process-sensitivity model. Identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout. Moreover, using the process-sensitivity model to identify the problem area reduces the computational time required to identify the problem area.
REFERENCES:
patent: 6453457 (2002-09-01), Pierrat et al.
patent: 6539521 (2003-03-01), Pierrat et al.
patent: 6777138 (2004-08-01), Pierrat et al.
patent: 6904587 (2005-06-01), Tsai et al.
patent: 6964032 (2005-11-01), Liebmann et al.
patent: 2002/0164065 (2002-11-01), Cai et al.
patent: 2003/0046654 (2003-03-01), Bodendorf et al.
patent: 2003/0121021 (2003-06-01), Liu et al.
patent: 2005/0037267 (2005-02-01), Yamazoe et al.
patent: 0 307 726 (1989-03-01), None
“Detailed Placement for improved Depth of Focus and CD Control”, by Puneet Gupta, IEEE, 2005.
“Characterization of Assist Features on impact of mask error enhancement factors for sub- 0.13um techology”, by Sia Kim Tan et al., 21stAnnual BACUS Symposium on Photomask Technology, Proceedings of SPIE, vol. 4562, 2002, pp. 1000-1007.
U.S. Appl. No., entitled “Permit for Controlling Access to Services in Protected Memory Systems,” to Efrem Lipkin and Theodore C. Goldstein, Filed Jun. 18, 1998, U.S. Appl. No. Not Yet Assigned.
Melvin, III Lawrence S.
Shiely James P.
Chiang Jack
Doan Nghia M.
Park Vaughan & Fleming LLP
Synopsys Inc.
LandOfFree
Method and apparatus for identifying a manufacturing problem... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for identifying a manufacturing problem..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for identifying a manufacturing problem... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3722015