Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2000-12-27
2003-09-02
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S135000
Reexamination Certificate
active
06615334
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing input/output I/O data management with an I/O buffer in a compressed memory subsystem.
DESCRIPTION OF THE RELATED ART
Computers and computer systems include a main memory that advantageously stores data in a compressed format. In a compressed memory system it is desirable to minimize memory latency and to provide improved efficiency performance.
It is desirable to provide an improved method and apparatus for implementing I/O data management in a compressed memory subsystem.
A need exists for a method and apparatus for implementing I/O data management with an I/O buffer in a compressed memory subsystem. It is desirable to provide such a method and apparatus for implementing I/O data management with an I/O buffer in a compressed memory subsystem that minimizes memory latency and provides improved efficiency performance.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method and apparatus for implementing I/O data management with an I/O buffer in a compressed memory subsystem. Other important objects of the present invention are to provide such method and apparatus for implementing I/O data management with an I/O buffer substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. An identified command is checked for an IOB flush condition. Responsive to no identified IOB flush condition, the identified command is checked for an IOB hit. Responsive to an identified IOB hit, a next expected I/O store to a cacheline for the IOB hit is incremented.
In accordance with features of the invention, I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.
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Allison Brian David
Clark Scott D.
Ellis Kevin L.
International Business Machines - Corporation
Pennington Joan
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