Method and apparatus for high speed testing of latch based...

Details Method and apparatus for high speed testing of latch based... Method and apparatus for high speed testing of latch based...

2007-06-12

2007-06-12

Decady, Alber (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S730000, C714S731000

Reexamination Certificate

active

10901609

ABSTRACT:
A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.

REFERENCES:
patent: 5394403 (1995-02-01), Klein
patent: 5761489 (1998-06-01), Broseghini et al.
patent: 5878055 (1999-03-01), Allen
patent: 6097664 (2000-08-01), Nguyen et al.
patent: 6574762 (2003-06-01), Karimi et al.
patent: 2004/0148554 (2004-07-01), Dervisoglu et al.
Vida-Toku et al., “Designing for Scan Test of High Performance Embedded Memories”, Aug. 1998, IEEE, pp. 101-108.
Zarrineh et al., “Automatic Insertion of Scan Structure to Enhance Testability of Embedded Memories, Cores and Chips”, Apr. 26-30, 1998, Proceeding of the 16th IEEE VLSI Test Symposium, pp. 98-103.

Affiliated with

Also associated with

Rating

Method and apparatus for high speed testing of latch based... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for high speed testing of latch based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for high speed testing of latch based... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3875354