Method and apparatus for high-speed data transmission bus...

Details Method and apparatus for high-speed data transmission bus... Method and apparatus for high-speed data transmission bus...

1998-12-14

2001-08-28

Etienne, Ario (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S120000, C714S030000

Reexamination Certificate

active

06282592

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of data transmission, more particularly to the entrainment required to adjust a high-speed data transmission bus in order to compensate for both internal and external delays.
BACKGROUND OF THE INVENTION
High-speed data communication systems have a need for improved maintenance of primary clock timing and synchronization of data carried by high-speed data buses. In a co-pending Patent Application entitled “Parallel Data Bus Integrated Clocking and Control” by John Gordon Hogeboom and assigned to Northern Telecom Limited, a high-speed parallel data bus having a single integrated signal path carrying both synchronous clock information and control data is disclosed. In this invention, the clock signal is transmitted at a lower rate, and only a primary edge, for example the falling edge, is used to control the timing of a phase-locked loop (PLL), which can then regenerate all required equal or high-rate clocks with required stability and phase relations. By using only timing increments of one bit time for the clock signal high and low periods, the same transmission media and interfaces may be used for the clock as are normally used for the associated data stream or streams. Furthermore, the alternate edge of the signal is independently modulated in increments of one data bit time to carry control data. Control data transmitted in this way, integrated with the clock signal, may be used in a process of adjusting or “trimming” delays of data from two or more sources multiplexed onto a data line. At the receiving end of the bus, the delays are adjusted in accordance with the control data, so that the various multiplexed data streams will align with each other in time at data receivers used to recover the bit streams. The clock signal is an ideal signal to carry such control data, since it must already connect to all transmitters and receivers, and because it directly provides the timing information needed to optimally recover the data it carries. In summary, the invention by John Gordon Hogeboom provides efficient means for achieving both a synchronous clock and a control data channel in a single signal path used with a high-speed parallel data bus, where the bus is implemented in a more compact and flexible manner than existing buses and achieves the maximum speed capability and/or the maximum margins for a given speed requirement.
An important issue for such a high-speed data bus is the transmission delays which occur both internally and externally to the bus itself. The term “entrainment” refers to the sampling and comparing of data which takes place at both the transmitting and receiving ends of the bus in order to regulate these delays and ensure the correct alignment of the data. For example, assume that 8 sources, each receiving 4 serial bits and outputting a 4 bit wide bus, all output their data at what they believe is the same time in order to form a 32 bit wide data bus. The correct format for the output over 6 clock cycles is:
S1
S2
S3
S4
S5
S6
S7
S8
cc1
0000
0000
0000
0000
0000
0000
0000
0000
cc2
0000
0000
0000
0000
0000
0000
0000
0000
cc3
0000
0000
0000
0000
0000
0000
0000
0000
cc4
1111
1111
1111
1111
1111
1111
1111
1111
cc5
0000
0000
0000
0000
0000
0000
0000
0000
cc6
0000
0000
0000
0000
0000
0000
0000
0000
Unfortunately, due to circuit board routing and varying environmental conditions, such as temperature, over time the 32 bits may become out of step with each other. Some of the bits may be early, while others may be late. The sampled and merged 32 bit bus may look like the following instead:
S1
S2
S3
S4
S5
S6
S7
S8
cc1
0000
0000
0000
0000
0000
0000
0000
0000
cc2
0000
0000
0000
0000
0000
0000
0000
0000
cc3
0000
0001
0000
0000
0000
1100
0000
0000
cc4
0011
1110
1111
1011
1110
0011
1110
1111
cc5
1100
0000
0000
0100
0001
0000
0001
0000
cc6
0000
0000
0000
0000
0000
0000
0000
0000
It is through entrainment that this incorrectly timed output can be realigned into the correct format.
The entrainment takes place at the hardware devices which use the high-speed data bus to transmit and receive data, for example a chip on an integrated circuit board, whereby such a device must include multiple high-speed connections. In general, for each high-speed connection, a bidirectional data pad cell within the hardware device is capable of both transmitting data to and receiving data from the connection. In the former case, the data pad cell is also referred to as a driver, whereas in the latter case, the data pad cell is also referred to as a receiver. In order to perform entrainment in the receive direction, the data pad cell must sample incoming data near the center of the data eye pattern. In order to do this, the pad must be able to control the sampling point to within a fraction of a bit time. Typically, the data pad cells of a device do contain such a sampling circuit, controlled by the device core, to allow the bit sample point to be fine grain adjusted. This adjustment consists in shifting the sample point whenever circuit board routing and various environmental factors cause a shift in the incoming data. Unfortunately, existing sampling circuitry lacks the ability to measure and control this adjustment from the core of the terminal device. Without this ability, the entrainment of a high-speed data transmission bus by such a device is much more complex and expensive. A similar situation occurs in the transmit direction.
Existing methods for performing the entrainment of a high-speed data transmission bus include reversing the data bus to return entrainment status, and providing entrainment signaling via a separate bus channel. Unfortunately, such methods have important disadvantages, such as complex hardware which can not be altered once cast in silicon, and the requirement for additional dedicated device I/O pins, to be used only for entrainment control and status feedback.
The background information provided above shows that there exists a need in the industry to provide an improved system and method for entraining a high-speed data transmission bus, in order to correct the data misalignment caused by the internal and external transmission bus delays.
SUMMARY OF THE INVENTION
The present invention is directed to the entrainment of a high-speed data transmission bus. Such entrainment is useful to compensate for the internal and external transmission delays which cause the misalignment of data being received or transmitted over the bus.
The present invention is particularly useful in applications where the high-speed data transmission bus to be entrained is an inter-device bus on a Printed Circuit Board (PCB), where the PCB supports the JTAG standard. This standard allows for internal device testing of logic and memory, plus external PCB level connectivity, and includes a JTAG master device responsible for operating the different JTAG scan modes for the entire PCB and also for performing the bus entrainment procedure. Specifically the JTAG master device controls multiple JTAG slave devices, one of which is present on each hardware device on the PCB. One important feature of the JTAG standard is that none of the JTAG scan operations may be run by the JTAG master device while a hardware device, such as a chip, is in normal operation since the scanning of internal data will destroy all information previously saved in the internal memory elements (flip-flops).
In summary, the invention provides for use of the JTAG master to perform bus entrainment after any initial diagnostic procedure, such as the power up scan, has completed, since the PCB JTAG master device serves no useful function once out of scan mode, also referred to as diagnostic mode. A novel mode of operation is supported by the JTAG master device, in addition to the scan or diagnostic mode, specifically a bus entrainment mode. This mode is only enabled when suitable conditions exist, i.e. when the PCB is in normal operation and the JTAG master device is out of the diagnostic mode. When the JTAG master is in entrainment mode, the use of a JTAG scan chain as an

Affiliated with

Also associated with

Rating

Method and apparatus for high-speed data transmission bus... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for high-speed data transmission bus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for high-speed data transmission bus... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2436613