Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-03-24
2001-09-18
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S743000, C438S744000
Reexamination Certificate
active
06291361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates, generally, to etching methods and apparatus for deep sub-micron semiconductor fabrication and, more particularly, to methods and apparatus for plasma etching both metal and inorganic layers in a single chamber.
2. Background Art and Technical Problems
Recent advances in semiconductor processing technology have led to the development of integrated circuit devices employing sub-micron and even deep sub-half-micron feature sizes. Deep sub-micron technologies, involving critical dimensions or feature sizes of less than 0.35 microns, require photo lithographic processes which employ progressively smaller incident wavelengths during the exposure process.
In addition, deep sub-micron feature sizes have spawned the development of sophisticated new photoresist recipes for use with these smaller wavelengths.
Deep sub-micron line widths also tend to drive a reduction in the thickness of the photoresist layers in order to maintain acceptable aspect ratios for the photoresist patterns. However, the use of thinner photoresist pattern layers has resulted in undesired erosion of the patterned microelectronic structure during the metal etch process.
Presently known attempts to preserve the integrity of the microelectronic structures in the presence of thin photoresist layers typically involve the use of metallic barrier layers, such as titanium nitride (TiN), in the metal stack. In addition, organic anti-reflection coating (ARC) layers have been employed on top of metallic barrier layers to help preserve the structural integrity of the photoresist pattern structures. Prior art practice has also utilized an oxide layer prior to the organic ARC layer to function as a hard mask. However, many of the different layers utilized in the prior art require different etching chemistries and etching tools thereby increasing processing time as well as equipment needed for fabricating semiconductor devices.
Although the use of these organic or metallic ARC layers has improved the integrity of the photoresist pattern structures, as well as the integrity of the resulting microelectronic structures, erosion of the patterned microelectronic structure may still occur in the case where all of the photoresist layer erodes away during metal etching, particularly when an organic ARC layer is used in the metal stack without an oxide hard mask.
Alternatively as contemplated by part of the present invention, an inorganic ARC layer may be used in the metal stack which provides a single optimized film that functions both as an antireflective coating, for preserving the structural integrity of the photoresist pattern strictures, and as a hard mask. Unlike the organic ARC layers and metal layers, inorganic ARC layers are typically etched with fluorine based chemistries. Since the process for etching the photoresist and the ARC layer, and the process for etching the metal layer, typically employ different etching tools which are specifically designed to optimize their respective etching processes and etching solution chemistries, the number of process steps and cycle time are increased.
Accordingly, there is a need for composite structures and manufacturing processes that accommodate smaller exposure wavelengths and thinner photoresist layers without jeopardizing the integrity of the microelectronic structures. In addition, there is also a need for composite structures and manufacturing processes which function to decrease the cost and complexity of the semiconductor fabrication process while increasing its efficiency.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a metal layer upon which photoresist patterns are developed comprises a sandwiched metal stack having a layer of conducting metal (aluminum, titanium, and the like) bounded by an upper thin-film ARC layer and a bottom thin-film barrier layer, wherein at least the top layer is composed of an inorganic dielectric substance. The use of an inorganic dielectric top ARC layer facilitates use of thinner photoresist layers while preserving the integrity of the photoresist pattern for deep sub-micron feature sizes. In addition, the inorganic ARC layer functions as a hard mask during the metal etch process, further enhancing the integrity of the metallic microelectronic strictures even as the photoresist is eroded during the metal etch process.
In accordance with a further aspect of the present invention, the inorganic dielectric layer may be applied utilizing a chemical vapor deposition (CVD) process. In accordance with a particular preferred embodiment, the inorganic dielectric ARC layer may be applied in a plasma enhanced CVD (PECVD) chamber.
In accordance with a further aspect of the present invention, the use of PECVD deposition techniques permits the application of the dielectric layer in a conformal manner, i.e., a uniform thickness of the dielectric may be applied to surfaces which are not perfectly planar, for example surfaces which contain a layer of microelectronic structures. This is a distinct advantage over prior art systems, wherein organic ARC layers are typically applied using a spin coat technique.
In accordance with a further aspect of the present invention, the etch selectivity of the metal etch medium is greatly enhanced in that the inorganic ARC is less susceptible to erosion during the metal etch process than prior art organic or metallic ARC layers.
In accordance with yet a further aspect of the present invention, the inorganic dielectric layer may be incorporated into the interconnect structure, without having to be removed in a subsequent processing step.
In accordance with a still further aspect of the present invention, the process of etching the inorganic dielectric layer down to the metal layer may be performed in the same tool within which the metal etching process is performed, thereby eliminating the need to change tooling between the dielectric etching step and the metal etching step.
In accordance with yet a further aspect of the present invention, the inorganic dielectric ARC layer may be etched using a fluorine based etching chemistry, immediately followed by the in-situ transition to a chlorine based etching process for the metal etching step.
Various other aspects and advantages of the present invention are set forth with particularity in the detailed description of preferred exemplary embodiments.
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Berg Michael J.
Brongo Maureen R.
Hsia Shao-Wen
Chen Kin-Chan
Conexant Systems Inc.
Hiteshew Felisa
Snell & Wilmer L.L.P.
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