Method and apparatus for high performance transistor devices

Details Method and apparatus for high performance transistor devices Method and apparatus for high performance transistor devices

1998-11-17

1999-11-09

Trinh, Michael

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438299, 438305, 438947, 438481, H01L 213205, H01L 21336

Patent

active

059813636

ABSTRACT:
The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a semiconducting substrate, and forming a layer of polysilicon above the layer of dielectric material. The method further comprises forming a layer of silicon nitride or silicon oxynitride above the layer of polysilicon, and patterning said layer of polysilicon and layer of silicon nitride or silicon oxynitride to define an opening and expose a sidewall surface of the polysilicon layer. The method continues with the growth of a lateral extension of the polysilicon layer and the oxidation of the extension. The method concludes with the patterning of the polysilicon layer to define a gate conductor, and the formation of source and drain regions in the substrate.

REFERENCES:
patent: 4061530 (1977-12-01), Hosack
patent: 4083098 (1978-04-01), Nicholas
patent: 4312680 (1982-01-01), Hsu
patent: 4313782 (1982-02-01), Sokoloski
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4445267 (1984-05-01), De La Moneda et al.
patent: 4999314 (1991-03-01), Pribat et al.

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