Method and apparatus for high-efficiency operation of a...

Static information storage and retrieval – Systems using particular element – Capacitors

Reexamination Certificate

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C365S205000, C365S203000

Reexamination Certificate

active

07599212

ABSTRACT:
The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.

REFERENCES:
patent: 5042011 (1991-08-01), Casper et al.
patent: 5280205 (1994-01-01), Green et al.
patent: 5627785 (1997-05-01), Gilliam et al.
patent: 6608794 (2003-08-01), Yoshioka
patent: 2003/0174533 (2003-09-01), Ito

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