Method and apparatus for hierarchical clock tree analysis

Details Method and apparatus for hierarchical clock tree analysis Method and apparatus for hierarchical clock tree analysis

2002-08-08

2004-02-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06687889

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains generally to integrated circuits, and more particularly, to a method for accurately analyzing clock timing in a point-to-point manner in a clock tree.
BACKGROUND OF THE INVENTION
Clock networks on CMOS integrated circuits have long been a source of difficulty to integrated circuit designers due to the importance of minimizing skew between clock inputs. A typical integrated circuit includes a clock tree which distributes one or more clock signals throughout the chip to clocked elements. A primary goal of a clock tree is to minimize clock skew between clocked elements. Since all clocked elements on a given tree are driven from one net with a clock spine, skew is caused by differing interconnect lengths and loads.
Clock skew represents a fraction of the clock period that cannot be used for computation. A clock skew of 500 ps with a 200 MHz clock means that 500 ps of every 5 ns clock cycle, or 10 percent of the performance is wasted. That is, clock skew may reduce the time allowed for certain logic paths within the design, and thus may reduce the performance of the design. Thus, for high performance designs that have strict timing requirements, it is often critical to minimize clock skew.
FIG. 1
is a diagram illustrating a reduction in the effective clock period between registers caused by clock skew. An illustrative timing path is shown at
10
, and a corresponding timing diagram therefore is shown at
30
. The timing path includes a first rising edge triggered register
22
a
receiving data D
a
from a first input/output pad
20
a
, and a second rising edge triggered register
22
b
receiving data D
b
from a second input/output pad
20
b
. The first register
22
a
is clocked by a first clock signal CLK
a
and the second register
22
b
is clocked by a second clock signal CLK
b
.
With reference to the timing diagram
30
, the input clock CLK is shown at
24
. The first clock signal CLK
a
and the second clock signal CLK
b
are generated from the input clock signal CLK
24
via a clock tree or the like. The timing diagram
30
shows that the first clock signal CLK
a
is skewed relative to the second clock signal CLK
b
, as shown by t
skew
. A large clock skew t
skew
may be caused by an improperly designed clock tree.
On the rising edge of the first clock signal CLK
a
, the first register
22
a
may transfer data Q
a
from input D
a
. On the rising edge of the second clock signal CLK
b
, the second register
22
b
may transfer data Q
b
from input D
b
. When the subsequent logic (not shown) is designed to receive and use the latched data Q
a
and Q
b
simultaneously, the clock skew t
skew
is clearly problematic.
Because of the clock skew t
skew
between the first and second clock signals CLK
a
and CLK
b
, the effective clock period T
eff
between the rising edges CLK
a
and CLK
b
is less than the clock period T
period
. This effectively reduces the time allowed for the data to pass through subsequent logic before receiving the next incoming data, and thus may reduce the effective maximum frequency of the circuit.
Clock skew may have a number of other detrimental effects on the performance of a circuit design. For example, clock skew may cause hold time violations when only a small amount of logic is provided between registers causing malfunction of the circuit. Further, clock skew may cause communication problems between integrated circuits. It should be recognized that these are only illustrative examples of effects that clock skew may have on a system.
For the above reasons, a primary goal of a clock tree is to minimize clock skew between clocked elements. As shown above, clock skew may reduce the effective clock period for certain logic paths within the design, and thus may reduce the performance of the design. For high performance designs that have strict timing requirements, clock skew may consume a substantial portion of the total clock period.
Clock trees may be balanced or unbalanced. Balanced clock trees distribute a number of clock drivers symmetrically and evenly placed on the integrated circuit die. In a balanced tree, the distance between each clock driver and its receiving element is preferably identical, and the load on each driver is matched. Balanced clock trees find suitable application in integrated circuits that are formed with functional blocks characterized by substantially similar loads, for example, memory chips formed with symmetrically balanced memory arrays.
By contrast, unbalanced clock trees distribute clock drivers in a non-symmetrical manner throughout the integrated circuit, generally with higher concentrations of clock drivers where the load is higher and lower concentrations of clock drivers where the load is smaller. Unbalanced clock trees are often utilized in complex circuits that are designed in a functionally hierarchical manner using a plurality of different functional blocks of differing loads. Unbalanced clock trees are typically used in integrated circuits that are partitioned into different functional blocks (and possibly to be designed by different groups of designers).
In the design cycle of a chip with a balanced design, the clock network is typically pre-placed on the integrated circuit die prior to placement of functional logic blocks. This scheme has a number of limitations. First, the clock buffering circuit may interfere with ideal block placement on the chip. This means that area or timing may need to be sacrificed. Second, any smaller blocks than the average will have a larger clock driver than is needed, possibly increasing the amount of power required. This scheme may waste chip resources.
In the design cycle of a chip with an unbalanced design, the clock network is normally added after determining where the appropriate buffers need to be located. This scheme also has a number of limitations. First, it prevents simulation of the clock network until all layers of the hierarchy are complete. This means that a parent block made up of one or more children blocks cannot be simulated until all of its children blocks are complete. As a result, the entire design must be complete before simulation can occur. If, as a result of simulation, it is discovered that one or more clock routes must be adjusted to meet the clock skew requirements, the final artwork is delayed until the layer(s) requiring adjustment are reworked, and the entire adjusted artwork is resimulated. This scheme is clearly time-consuming and costly.
Second, as process generations have advanced, the contributions of parasitic resistance and capacitance of the clock tree routing traces has become a significant portion of the overall clock skew. In order to properly analyze and simulate the performance of the clock network, the clock skew must be determined with sufficient accuracy such that it matches that of the actual design within predetermined error limits. The accuracy level of current circuit simulation tools is typically dependent on the size of the circuit to be analyzed. In other words, a relatively simple circuit with ten to a few hundred nets may be simulated with fairly high accuracy; in contrast, the accuracy level decreases when the number of nets is increased to thousands (or much higher numbers) of nets.
Accordingly, a need exists for an improved method for accurately analyzing and simulating clock performance of a clock network in a functionally hierarchically designed integrated circuit.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for accurately analyzing the timing of an unbalanced clock network on a piecemeal basis in an integrated circuit clock tree. The present invention allows an entire integrated circuit clock network to be accurately analyzed and simulated on a functional-level basis without requiring higher-level functions to be completed.
The invention applies to functionally hierarchical integrated circuit designs wherein the functionality of the chip is partitioned into different functional blocks located on different functionality levels. More particula

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