Method and apparatus for hardware timing optimizer

Details Method and apparatus for hardware timing optimizer Method and apparatus for hardware timing optimizer

2005-01-18

2008-10-14

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000, C714S030000

Reexamination Certificate

active

07437591

ABSTRACT:
A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.

REFERENCES:
patent: 5452323 (1995-09-01), Rosen
patent: 5487092 (1996-01-01), Finney et al.
patent: 5692166 (1997-11-01), Milhizer et al.
patent: 5793800 (1998-08-01), Jylha et al.
patent: 6538469 (2003-03-01), Nguyen et al.
patent: 6671847 (2003-12-01), Chao et al.
patent: 6834367 (2004-12-01), Bonneau et al.
patent: 6898741 (2005-05-01), Muljono et al.
patent: 6904375 (2005-06-01), Sabih et al.
patent: 7049839 (2006-05-01), Hsiao et al.
patent: 7143312 (2006-11-01), Wang et al.
patent: 7159092 (2007-01-01), Johnson et al.
patent: 2003/0120989 (2003-06-01), Zumkehr
patent: 2003/0208717 (2003-11-01), Klotchkov et al.
patent: 2004/0268193 (2004-12-01), Nishida et al.
patent: 2005/0047538 (2005-03-01), Jaussi et al.
patent: 2006/0056498 (2006-03-01), Clancy et al.
patent: 2006/0107154 (2006-05-01), Bansal et al.

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