Method and apparatus for hardening current steering logic to sof

Details Method and apparatus for hardening current steering logic to sof Method and apparatus for hardening current steering logic to sof

1995-06-29

1997-02-04

Westin, Edward P.

Electronic digital logic circuitry

Reliability

Redundant

326 10, 326 31, 326127, H03K 19003, H03K 1900

Patent

active

056002602

ABSTRACT:
A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

REFERENCES:
patent: 3818243 (1974-06-01), McMahon
patent: 4593249 (1986-06-01), Arita et al.
patent: 4617475 (1986-10-01), Reinschmidt
patent: 4621201 (1986-11-01), Amdahl et al.
patent: 5436572 (1995-07-01), Sugiyama

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