Method and apparatus for handling transient memory errors

Details Method and apparatus for handling transient memory errors Method and apparatus for handling transient memory errors

2005-08-16

2005-08-16

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S042000, C714S053000, C714S054000

Reexamination Certificate

active

06931571

ABSTRACT:
Method and apparatus for managing memory of a data processing system. In one embodiment, memory objects are allocated in response to memory allocation requests. Each object has an associated plurality of addresses. Type-identifier codes are respectively stored in association with the memory objects. Upon detection of a transient memory error at a memory address a recovery action is selected and performed based on the type-identifier code of the object that is associated with the erring memory address.

REFERENCES:
patent: 6012157 (2000-01-01), Lu
patent: 6530036 (2003-03-01), Frey, Jr.
patent: 6609184 (2003-08-01), Bradshaw et al.
patent: 6622269 (2003-09-01), Ngo et al.
patent: 6647517 (2003-11-01), Dickey et al.
patent: 6665689 (2003-12-01), Muhlestein
patent: 6697971 (2004-02-01), Dwyer
patent: 6701451 (2004-03-01), Cohen et al.
patent: 6715036 (2004-03-01), Burton et al.

Affiliated with

Also associated with

Rating

Method and apparatus for handling transient memory errors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for handling transient memory errors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for handling transient memory errors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3520790