Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-08-23
2005-08-23
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S158000, C711S151000, C710S040000, C710S036000
Reexamination Certificate
active
06934823
ABSTRACT:
A method of handling memory read return data from different time domains includes determining a number of distinct memory device ranks. A time domain for each of the distinct memory device ranks is determined. A transaction is scheduled based on the time domain for each of the distinct memory device ranks so that at least one of data collisions and out-of-order data returns are prevented.
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Dodd James M
Williams Michael W
Bataille Pierre-Michel
Pillsbury Winthrop Shaw & Pittman LLP
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