Method and apparatus for handling failure in address line

Details Method and apparatus for handling failure in address line Method and apparatus for handling failure in address line

2009-04-27

2010-12-14

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000, C365S201000

Reexamination Certificate

active

07853838

ABSTRACT:
An address line failure handling apparatus includes a failed address line specifying unit that examines the address line connected to each bit and specifies a failed address line, an address line substituting unit in which an upper address line connected to an upper bit of the memory is connected with a branch address line branched off from a lower address line connected to a lower bit other than the upper bit, and that switches between an input from the upper address line and an input from the branch address line, and outputs any of the inputs to the upper bit, and an address line substitution instructing unit that instructs the address line substituting unit to switch from the upper address line to the branch address line branched off from the failed address line when the failed address line is specified.

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International Search Report issued Jan. 16, 2007 in corresponding International Patent Application PCT/JP2006/321566.

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