Method and apparatus for handling cyclic buffer access

Details Method and apparatus for handling cyclic buffer access Method and apparatus for handling cyclic buffer access

2005-09-06

2005-09-06

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S110000, C711S202000, C711S209000

Reexamination Certificate

active

06941441

ABSTRACT:
A first logical memory address identifies a first logical memory location that is outside of a logical buffer space. The first logical memory address is received and is translated into a second logical memory address that identifies a second logical memory location that is within the logical buffer space.

REFERENCES:
patent: 5535412 (1996-07-01), Nadehara
patent: 5584038 (1996-12-01), Papworth et al.
patent: 5623621 (1997-04-01), Garde
patent: 5943693 (1999-08-01), Barth
patent: 6560691 (2003-05-01), Chen
patent: 6807615 (2004-10-01), Wong et al.
patent: 2002/0156990 (2002-10-01), Chen

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