Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-12-08
2003-07-15
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S210000, C712S233000
Reexamination Certificate
active
06594750
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to virtual memory translation caching in a computer system and more specifically to handling an accessed bit in a page table entry.
BACKGROUND OF THE INVENTION
In a computer system, instructions and data are stored in a memory device until they are needed. The memory device is organized according to an addressing scheme to allow the instructions and data to be located by specifying an address. However, while the memory device is organized into a plurality of physical addresses, it is often useful for a processor to consider the instructions and data to be organized according to a different addressing scheme, denoted by virtual addresses. The virtual addresses may be converted to physical addresses to allow the instructions and data to be accessed in the memory device.
A translation lookaside buffer (TLB) structure may be used to provide a cache for translation of virtual addresses to physical addresses. The TLB structure includes a plurality of upper-level page tables, also referred to as page directories, that contain upper-level page table entries, also referred to as page directory entries. The TLB structure also includes a plurality of lower-level page tables that contain lower-level page table entries. The upper-level page table entries serve as pointers to the plurality of lower-level page tables and the lower-level page table entries serve as pointers to pages of data in the memory device.
FIG. 1
is a block diagram illustrating the relationship between a processor, a TLB structure, and memory. Processor
101
is coupled to and communicates in virtual addresses with TLB structure
102
. TLB structure
102
is coupled to and communicates in physical addresses with main memory
103
. Alternatively, processor
101
may communicate directly with main memory
103
.
A virtual memory system makes it possible to generate addresses for address space in excess of that actually supported by physical memory devices. In such a virtual memory system, virtual memory pages are loaded into available physical memory devices as memory accesses are made to memory locations within those virtual memory pages. Other virtual memory pages that are no longer needed are written to a larger, but often slower, storage device, for example a hard disk drive. To manage the paging of such a virtual memory system, certain indications about the status of the virtual memory system are provided.
If changes are made that affect the TLB structure
102
, a “dirty” indication is provided to processor
101
so that processor
101
can maintain consistency between the TLB structure
102
and the main memory
103
. An “accessed” indication is used by the operating system running on processor
101
to check memory usage. The “accessed” indication indicates a recent memory access. An electrical circuit provides the “accessed” indication, for example by asserting an “accessed” bit for an accessed page table entry in memory page tables from which the TLB structure
102
is loaded. Upon the first access to that accessed page table entry, the accessed bit is set and written back into main memory. “Accessed” indications can be used, for example, to implement a least-recently-used (LRU) replacement strategy for main memory pages.
The operating system running on processor
101
identifies accessed page table entries based on the “accessed” indications and resets the “accessed” indications, for example by deasserting the “accessed” bits. In the prior art, electrical circuits were provided to handle the assertion and deassertion of “accessed” indications. However, such electrical circuits occupy substantial space on an integrated circuit die. As the complexity of integrated circuits used in computers has increased, the amount of space on an integrated circuit die for such electrical circuits can no longer be afforded, as that space is now needed for other circuitry. Thus, the use of electrical circuits to handle the assertion and deassertion of “accessed” indications is no longer feasible.
Thus, a method and apparatus is needed to allow efficient handling of an accessed bit in a page table entry.
REFERENCES:
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5873123 (1999-02-01), Patel et al.
patent: 6003123 (1999-12-01), Carter et al.
patent: 6038631 (2000-03-01), Suzuki et al.
patent: 6101590 (2000-08-01), Hansen
patent: 6199152 (2001-03-01), Kelly et al.
patent: 6378067 (2002-04-01), Golliver et al.
ATI International SrL
Chace C. P.
Vedder Price Kaufman & Kammholz
Yoo Do Hyun
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