Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-11-29
2001-05-29
Lam, Tuan T. (Department: 2816)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C026S098000
Reexamination Certificate
active
06239620
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to logic circuits in general, and in particular to circuits for generating true/complement signals. Still more particularly, the present invention relates to a circuit for generating low skew true/complement signals.
2. Description of the Prior Art
Dual-rail systems are commonly used in static and dynamic logic circuits, such as adders, multipliers, sense amplifiers, etc. A dual-rail system typically requires the generation of true signal inputs and their complementary signal inputs.
For static logic circuits, a complementary signal input can conveniently be generated by passing a true signal input through an inverter. However, for dynamic logic circuits, such as domino circuits, a more sophisticated true/complement signal generator is commonly required. This is because dynamic logic gates generally have shorter time delays than static logic gates, which is the reason why dynamic logic circuits generally have a higher speed operation relative to their static counterparts.
Typically, dynamic logic circuits have a precharge phase and an evaluation phase. To ensure correct operation, dynamic logic circuits require that the input signal received a dynamic logic gate must either be stable before the beginning of the evaluation phase, or transition in only one predetermined direction during the evaluation phase. For example, a dynamic logic gate may require that an input signal be at a low voltage level during the precharge phase, and thus only low-to-high transitions are allowed during the evaluation phase. Hence, dynamic logic circuits in a dual-rail system tend to require their true and complement signal inputs to having more balanced timing. The present disclosure provides an improved true/complement signal generator for generating low skew true/complement signals to be used in high-speed dynamic logic circuits.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5179300 (1993-01-01), Rolandi et al.
patent: 5894229 (1999-04-01), Yamoka et al.
Aoki Naoaki
Dhong Sang Hoo
Kojima Nobuo
Silberman Joel Abraham
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Lam Tuan T.
Salys Casimer K.
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