Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-08-03
2008-03-18
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S309000, C710S313000
Reexamination Certificate
active
07346725
ABSTRACT:
A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.
REFERENCES:
patent: 5455915 (1995-10-01), Coke
patent: 5499346 (1996-03-01), Amini et al.
patent: 5778235 (1998-07-01), Robertson
patent: 5857085 (1999-01-01), Zhang et al.
patent: 5991833 (1999-11-01), Wandler et al.
patent: 6070215 (2000-05-01), Deschepper et al.
patent: 6101566 (2000-08-01), Woods et al.
patent: 6119192 (2000-09-01), Kao et al.
patent: 6145048 (2000-11-01), Klein
patent: 6199134 (2001-03-01), Deschepper et al.
patent: 6272642 (2001-08-01), Pole et al.
patent: 6360327 (2002-03-01), Hobson
patent: 6457091 (2002-09-01), Lange et al.
patent: 6704877 (2004-03-01), Cline et al.
patent: 6795883 (2004-09-01), Tsai
patent: 6834301 (2004-12-01), Hanchett
patent: 6839793 (2005-01-01), Ragland
patent: 7003607 (2006-02-01), Gulick
patent: 7010630 (2006-03-01), Pagan
patent: 2002/0023190 (2002-02-01), Peng
patent: 2002/0124197 (2002-09-01), Atkinson
patent: P2001-216390 (2000-02-01), None
Intel 815 Chipset Family: 82815P/82815EP Memory Controller Hub (MCH), Intel, Sep. 2001.
Morris Mano, “Computer System Architecture”, 1982, Prentice-Hall, Inc., 2nd Ed., pp. 59-61.
Jagan Jayaraj et al., “Shadow Register Architecture: A Mechanism to Reduce Context Latency”, College of Engineering Guindy, Anna University, Chennai, India, unknown date.
PCI Special Interest Group, “PCI-to-PCI Bridge Architecture Specification”, 1998, PCI Special Interest Group, Rev. 1.1, pp. 11-13 and 19-30.
Intel 440BX AGPset: 82443BX Host Bridge/Controller Specification Update, Intel Document No. 290639-006, Jan. 2001, pp. 1-48.
Intel 82371AB PIIX4, Intel 82371EB PIIX4E, Intel 82731MB PIIX4M Specification Update, Intel Document No. 297738-017, Jan. 2002, pp. 1-55.
Joshi Aniruddha P.
Munguia Peter R.
Wang Jennifer C.
Dang Khanh
Intel Corporation
Kacvinsky LLC
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