Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2000-04-28
2003-11-18
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
Reexamination Certificate
active
06651180
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to computer systems. More particularly, the invention relates to a mechanism for reducing timeout uncertainty associated with pending transactions.
BACKGROUND OF THE INVENTION
It is common for devices coupled in a computer system to communicate by exchanging transactions or requests. For example, an I/O device can initiate a transaction requesting data from a host I/O bridge. The host I/O bridge, in turn, can initiate a DMA transaction requesting the data from main memory. While the host I/O bridge is waiting for the requested data, the host I/O bridge can perform other tasks including initiating other DMA transactions. In order to prevent the host I/O bridge from waiting indefinitely for the requested data, a timeout mechanism is often used to indicate that an error has occurred when a response is not received within the timeout period. The host I/O bridge then handles the error according to the type of timeout.
One such timeout mechanism is a timeout counter. A timeout counter tracks the number of timeout periods that have lapsed since the transaction was initiated. The timeout counter consists of a number of bits, n, and can track 2
n
timeout periods. When the timeout counter reaches a predetermined threshold, an interrupt is set indicating that a timeout has occurred.
The number and length of the timeout periods is usually set based on the maximum expected response time for the transaction. In some applications, it is necessary for the timeout counter to indicate with reasonably accuracy the time at which the timeout occurs. However, this requirement is not always feasible.
In some applications, a single timeout counter is used to accommodate multiple transactions. Although this technique utilizes less circuitry, it does not accurately track the time at which the timeout occurs. The transactions are queued and the timeout starts once the transaction gets to the head of the queue. The time that the transaction waits in the queue is not tracked which affects the accuracy of the timeout.
In yet other applications, there is a timeout counter for each transaction. Although this produces a more accurate result, it has the drawback of requiring a considerable amount of circuitry. For example, for an application having 128 possible outstanding transactions where each timeout counter has 20 bits, there would have to be 2560 bits of counters. At times, this amount of circuitry is not feasible. Accordingly, there is a need to overcome these shortcomings.
SUMMARY OF THE INVENTION
In summary, the technology of the present invention pertains to a timeout mechanism that attempts to accurately track the time a timeout occurs while preserving the amount of circuitry and processing required to maintain this accuracy. In an embodiment of the present invention, the timeout mechanism is used to track requests for cache lines that are requested from an I/O bridge in a multiprocessor system.
The timeout mechanism includes a timeout control unit having a fetch state machine for each cache line entry. Each fetch state machine ensures that the outstanding fetch transaction for the associated cache line times out after a prescribed number of timeout periods have lapsed. Preferably, there are six timeout periods. The timeout periods are set at a relatively small interval so that when the timeout occurs, the timeout will have occurred within a smaller time frame which produces a more accurate result. If the fetch transaction times out, an error control unit is notified which handles the timeout appropriately.
Such accuracy is important in a system, such as the computer system described herein, which has a hierarchy of timeouts. The lowest priority timeouts have a shorter timeout period with the higher priority timeouts having a longer timeout period. Each succeeding level in the hierarchy has a longer timeout period than a preceeding priority level. The priority level scheme is set so that the lower priority devices shut down before the higher priority devices in the event of a system failure. If a lower priority component's timeouts are longer than expected, it can affect the shutdown order.
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Connolly Mark
Hartnett Clare T.
Hewlett-Packard Development Company LP.
Lee Thomas
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