Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-02
2005-08-02
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S738000
Reexamination Certificate
active
06925617
ABSTRACT:
A method generates a test pattern for an integrated circuit (IC) design using a functional verification program. The functional verification program includes a stimulus generator, an expected-response generator, and an interface defining ports of the IC design. The method includes (a) converting input ports in the interface into bi-directional in/out ports, (b) supplying stimuli to the converted in/out ports and original in/out ports in the interface by executing the stimulus generator, (c) sampling the stimuli supplied to the converted in/out ports and the original in/out ports, and (d) recording the sampled stimuli. The method may further include (e) creating bi-directional shadow ports in the interface, the shadow ports corresponding to the in/out ports and output ports of the IC design, (f) supplying expected responses to the shadow ports by executing the expected-response generator, (g) sampling the expected responses from the shadow ports, and (h) recording the sampled expected response.
REFERENCES:
patent: 6052809 (2000-04-01), Bowden
patent: 6675337 (2004-01-01), Tung et al.
Bayraktaroglu Ismet
Caty Olivier
Garbowski Leigh M.
Gunnison McKay & Hodgson, L.L.P.
Sun Microsystems Inc.
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