Method and apparatus for generating planarizing pattern and semi

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth from gaseous state combined with subsequent...

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39550014, 438626, 438631, 438645, 438697, G06F 1750

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active

059702389

ABSTRACT:
A dummy pattern is generated by enlarging a wiring pattern by a specified amount to generate an enlarged wiring pattern and deleting the overlapping portion of a first dummy original pattern composed of a group of squares with the enlarged wiring pattern. The dummy pattern is reduced by the specified amount to generate a reduced dummy pattern, which is enlarged by the specified amount to generate a planarizing pattern. The planarizing pattern is combined with the wiring pattern to generate a final pattern.

REFERENCES:
patent: 5341310 (1994-08-01), Gould et al.
patent: 5459093 (1995-10-01), Kuroda et al.
patent: 5488007 (1996-01-01), Kim et al.
patent: 5798298 (1998-08-01), Yang et al.
PTO 99-0312 (Translation of Japanese Patent Publication, Document No. 5-267,460, invented by Kitsukawa, published Oct. 15, 1993, translated Nov. 1998 by Schreiber Translations, Inc., 12 pages).
PTO 99-0311 (Translation of Japanese Patent, Document No. 8-160590, invented by Motoyama et al., published Jun. 21, 1996, translated by Schreiber Translations, Inc., 37 pages), Nov. 1998.
PTO 99-0391 (Translation of Japanese Published Unexamined (Kokai) Patent Application No. 6-61230, invented by Yamawaki, published Mar. 4, 1994, translated by Chisato Morohashi, USPTO Translation Branch, 7 pages), Nov. 5, 1998.

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