Method and apparatus for generating parity values

Details Method and apparatus for generating parity values Method and apparatus for generating parity values

2005-12-27

2005-12-27

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S807000

Reexamination Certificate

active

06981206

ABSTRACT:
A circuit for computing parity values is disclosed. The circuit includes a control decode unit. The control decode unit determines whether words received during a cycle correspond to more than one packet of data. The circuit includes a first parity processor. The first parity processor computes first parity sum values from first words associated with a first packet of data received during the cycle. The circuit includes a second parity processor. The second parity processor is capable of computing second parity sum values from second words associated with a second packet of data received during the cycle when the control decode unit determines that the data words correspond to more than one packet of data.

REFERENCES:
patent: 4295219 (1981-10-01), Draper et al.
patent: 4314350 (1982-02-01), Toy
patent: 5835511 (1998-11-01), Christie
patent: 6742159 (2004-05-01), Sakurai

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