Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-09-29
2009-10-06
Odom, Curtis B (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S229000, C375S230000, C375S231000, C375S232000, C375S233000, C375S371000
Reexamination Certificate
active
07599461
ABSTRACT:
Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.
REFERENCES:
patent: 2005/0265440 (2005-12-01), Sohn
patent: 2007/0253475 (2007-11-01), Palmer
Aziz Pervez M.
Sindalovsky Vladimir
Smith Lane A.
Agere Systems Inc.
Odom Curtis B
Ryan & Mason & Lewis, LLP
LandOfFree
Method and apparatus for generating one or more clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for generating one or more clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating one or more clock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4059110