Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Patent
1998-04-17
2000-02-22
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
G06F 106
Patent
active
060292520
ABSTRACT:
A multi-phase clock generator is implemented by a delay circuit that receives an input clock signal. The clock generator couples the input clock signal to a first clock output terminal and to a delay circuit. The delay circuit delays the input clock signal to produce a delayed clock signal, and the delayed clock signal is coupled to a second clock output terminal. The first and second clock signals coupled to the first and second clock output terminals are applied to a logic circuit that generates two clock signals and their compliments. These clock signals are used to clock a shift register on both the rising and falling edge of the input clock signal. The shift register may be used in a command buffer for a packetized DRAM, and one or more of the resulting packetized DRAMs may be used in a computer system.
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"Draft Standard for a High-Speed Memory Interface (SyncLink)," Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.
Heckler Thomas M.
Micro)n Technology, Inc.
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