Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-29
2001-06-12
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06247162
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a method and apparatus for generating layout data, and more particularly, to a method and device for generating layout data for optimizing external power supply wirings to function blocks in a semiconductor integrated circuit device.
In a conventional process for determining the external power supply wirings to function blocks for a semiconductor integrated circuit device, an external power network for external power wirings is generated based on information about an internal power network of each function block and information about the current consumption of each power supply terminal of each function block. The external power network includes resistance elements, sampled from the external power wiring pattern and having predetermined resistance values, and current sources connected to nodes of the external power wirings and having predetermined current consumption values. The external power network is analyzed using a matrix expression, for example, and based on the analysis results, the width and the wiring path of the external power wirings connected to the power supply terminals of each function block are determined.
However, if information about the internal power network or information about the current consumption of each power supply terminal of the function block is not included in the function block library data, it is difficult to lay out the external power wiring having an optimum width. Accordingly, if information about the function block is insufficient, it is desirable to obtain the current consumption of each power supply terminal in order to lay out the external power wiring having the optimum width.
Circuit simulations are used to obtain the current consumption. First, resistance elements are sampled from the layout data of the function block based on a gate length, gate width, and the wiring length between the nodes of the internal power wirings, and an equivalent circuit is generated from the sampled resistance elements. Then, the electrical operation simulation of the equivalent circuit is carried out and based on the simulation result, the current consumption in each power supply terminal of the function block is obtained. Further, based on the current consumption, an external power network is generated, and the external power network is analyzed. Then, based on the analysis result, the layout of the external power wirings is determined. This method accurately determines the current consumption. However, the circuit simulation is time-consuming.
Another method involves setting the same current consumption ratio for all of the power supply terminals of the function block. Because this method generates the external power network based on a set current consumption ratio, no circuit simulation is required.
However, the current consumption for the power supply terminals usually varies according to the arrangement position of a transistor as a current source. Accordingly, differences in current consumption are not reflected in the analysis result of the external power network. As a result, the layout of the external power wirings is not optimized.
It is an object of the present invention to provide a method and apparatus for laying out an optimized external power wiring pattern in a short time.
SUMMARY OF THE INVENTION
Briefly stated, a method is provided for generating layout data of external power wirings that supply a power supply voltage to a plurality of power supply terminals in each block provided in a semiconductor integrated circuit device. First, design information of the semiconductor integrated circuit device is acquired. The design information includes external power wiring layout information, block layout information, and block current consumption values. Then, a current consumption ratio for each power supply terminal of each block is calculated using the block layout information. The current consumption for each power supply terminal is calculated using the corresponding calculated current consumption ratio and the block current consumption value. Then, an external power network of the external power wirings is generated using the external power wiring layout information. The external power network is analyzed to calculate voltage and current values for a plurality of parts of the external power wirings. Then, a structure of the external power wirings is generated in accordance with the calculated voltage and current values.
Another aspect of the present invention provides a recording medium having recorded thereon computer readable program code for generating layout data of external power wirings that supply a power supply voltage to a plurality of power supply terminals in each block. The program includes the steps of the above method.
Yet another aspect of the present invention provides an apparatus for generating layout data of external power wirings that supply a power supply voltage to a plurality of power supply terminals in each block. The apparatus includes a memory for storing design information of the semiconductor integrated circuit device including external power wiring layout information, block layout information, and block current consumption values. A processor is connected to the memory and executes layout processing. The processor operates to calculate a current consumption ratio for each power supply terminal of each block using the block layout information, calculate the current consumption for each power supply terminal using the corresponding calculated current consumption ratio and the block current consumption value, and generate an external power network of the external power wirings using the external power wiring layout information. The processor further operates to analyze the external power network to calculate voltage and current values for a plurality of parts of the external power wirings, and generate a structure of the external power wirings in accordance with the calculated voltage and current values.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5648910 (1997-07-01), Ito
patent: 2-188943 (1990-07-01), None
patent: 4-107845 (1992-04-01), None
patent: 2521041 (1996-05-01), None
Fujine Eiji
Isoda Masahito
Nawa Takanori
Yuyama Hiroshi
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Phan Trong
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