Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-06-30
2002-05-21
Fears, Terell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S201000, C365S203000
Reexamination Certificate
active
06392936
ABSTRACT:
TECHNICAL FIELD
This invention relates to a memory architecture having a reduced value of settling time of its internal voltage references, and to a method of generating voltage references.
BACKGROUND OF THE INVENTION
Flash memory cells are programmed by applying appropriate voltage values to gate and drain terminals of the cells.
As shown in
FIG. 1A
, a flash type of memory architecture
1
includes a plurality of memory cells laid into a matrix
2
. The cell terminals are accessed by a row decoder
3
and a column decoder
4
, the latter being controlled by so-called program load devices
5
.
In particular, the row decoder
3
is supplied a first voltage reference VPCX directly, which is called row decode reference and obtained through a first adjuster
6
from a first high-voltage reference HV
1
, as output from a first voltage booster circuit
7
being in particular a charge pump circuit.
Likewise, the column decoder
4
is supplied a second voltage reference VPCY, called column decode reference and obtained through a second adjuster
7
from a second high-voltage reference HV
2
, as output from a second voltage booster circuit
9
being in particular a charge pump circuit. The program load devices
5
are supplied a program voltage reference VPD, which is obtained, through a third adjuster
10
, from a third high-voltage reference HV
3
as output from a third voltage booster circuit
11
being in particular a charge pump circuit.
As shown in
FIG. 1B
, a gate terminal G
1
of a selected memory cell
13
is connected to the row decode voltage reference VPCX through the row decoder
3
, and the cell drain terminal D
1
is connected to the program voltage reference VPD through a series of the column decoder
4
and the program load devices
5
.
This program voltage reference VPD is, therefore, to go through three tiers of pass transistors YN, YM and YO contained in the column decoder
4
. In order for these pass transistors YN, YM and YO to operate in the triode range, thereby minimizing the voltage drop across them, the column decode voltage reference VPCY is applied to the gate terminals of the pass transistors.
It is known to how obtain these voltage references VPCX, VPCY and VPD from boosted voltage references HV
1
, HV
2
and HV
3
, by means of the adjusters
6
,
8
and
10
, which use suitable operational amplifiers, as shown in
FIG. 2
for a generic high-voltage reference VPC obtained from a boosted voltage reference HV by means of an operational amplifier
14
.
A memory cell programming operation is usually preceded, and followed, respectively by two operations to verify the cell state, also known as the program verify operations. By these verify operations, a check is made of whether the cell requires one or more additional program pulses.
During these verify operations, the value of the row decode reference VPCX is less than that used during the program operations, while the value of the program voltage reference VPD remains substantially constant at about 1 Volt.
FIG. 3
shows plots vs. time of the voltage references VPCX, VPCY and VPD during a program operation.
For the memory cell programming operations, as well as the subsequent verifying operations, to be performed correctly, the high-voltage references VPCX and VPCY are first to attain desired values. This wait or settling time represents a technical loss, in that no operations can be carried out at the cell in the meantime.
Settling time is dependent on a capacitance (of up to 100 pF) associated with the row and column decoders
6
and
8
, as well as on the voltage booster devices
7
and
9
providing the boosted voltages HV
1
and HV
2
(in particular, from their equivalent output resistances, on the order of 10 k&OHgr;). In conventional devices, it may amount to a few microseconds.
Until now, no memory architecture existed with such structural and functional features as to allow settling time to be reduced, and overcome the drawbacks of similar prior devices.
SUMMARY OF THE INVENTION
Principles of embodiments of this invention include having the boosted voltage references paralleled to increase their charge capacity during predetermined operations to be performed at the memory cell. In particular, embodiments of the inventive memory architecture include suitable controlled switches associated with the boosted voltage references.
Based on these principles, embodiments of the invention include a memory architecture which has at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted voltage references are in turn connected to first, second and third adjusters adapted to provide respective first, second and third voltage references for the memory architecture. The memory architecture uses these voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. The boosted reference voltages can be coupled in parallel together by one or more switches during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of a first circuit node so as to shorten the settling time of the first voltage reference.
Embodiments of the invention also include a method of generating a plurality of boosted voltage references by means of a plurality of voltage booster circuits; adjusting the plurality of boosted voltage references by means of a plurality of adjusters to provide a plurality of voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture; and paralleling at least first and second high-voltage references during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively shorten the settling time of at least one in the plurality of voltage references.
The features and advantages of a memory architecture according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5051958 (1991-09-01), Arakawa
patent: 5250854 (1993-10-01), Lien
Maccarrone Marco
Mulatti Jacopo
Fears Terell W.
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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