Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2005-03-08
2005-03-08
Chace, Christian P. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S220000, C365S201000, C708S250000, C714S728000, C714S730000, C714S738000, C714S743000
Reexamination Certificate
active
06865660
ABSTRACT:
A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.
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Chace Christian P.
Dickstein , Shapiro, Morin & Oshinsky, LLP
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